Pcie 4.0 Specification

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PLDA, the company that designs and sells intellectual property (IP) cores and prototyping tools for ASICs and FPGAs, has optimized its ASIC intellectual property (IP) cores for the next generation of the ubiquitous and general purpose PCI Express® I/O specification, 4.0. PLDA’s proven 3.0 architecture enables easy migration to PCIe 4.0, with no interface changes necessary, and preserves existing behavior for seamless integration.

PLDA has over 20 years of experience in the design of IP cores for ASIC design, specializing in high-speed interface protocols and technologies, with a specific focus on PCIe. Over 6,200 customers have used PLDA cores for several hundred ASIC tapeouts.

PLDA released the first silicon proven PCIe 4.0 Controller IP and the first PCIe 4.0 development platform.

  • What is PCIe 4.0?

The PCI Special Interest Group (PCI-SIG) completed the PCIe 4.0 specification in 2017. Compared to PCIe 3.0, the data transfer rate doubles from 8 GT/s to 16 GT/s and allows a maximum net data rate of around 2 GByte/s per lane. PCIe 4.0 x16 then achieves almost 32 GByte/s. PCIe 4.0 is an embedded specification so it requires a motherboard and CPU that are PCIe 4.0 compliant. This means an AMD B550 or X570 chipset motherboard, or at the high end their AMD TRX40 Threadripper motherboards.

PCIe 4.0 is the next evolution of the ubiquitous and general purpose PCI Express I/O specification. The interconnect performance bandwidth is double that of the PCIe 3.0 specification achieving 16GT/s and compatibility with software and mechanical interfaces is preserved. PCIe 4.0 architecture is compatible with prior generations of PCIe technology.

To enable this evolution, PCI SIG has been working hard to follow a regular cycle that aims to double PCIe bandwidth every 4 years. PCIe is an Open Standard, directed by PCI SIG, a 22-year old group to allow companies to collaborate on thestandard development.
  • Who needs PCIe 4.0?
    • ​Big Data needs throughput

According to Gary King, Weatherhead University Professor, “The data flow so fast that the total accumulation of the past two years—a zettabyte—dwarfs the prior record of human civilization”. Internet, ubiquitous smartphone usage and increased marketing accelerated the Big Data revolution and the Internet of Things (IoT) will increase the needs for fast and efficient data management environments. More Throughput and Lower Power are necessary to prevent a bottleneck in the emergence of Big Data.

Specification
  • ​Networking applications

8-lane and 16-lane PCI Express 3.0 have the bandwidth required to handle a 40Gb Ethernet connection. However, using that many lanes raises cost, packaging, and power issues. Xbox companion for mac. A higher speed link requiring fewer lanes would be a much better implementation.

  • ​Storage Technologies need more Bandwidth

Data stream provided by PCIe 3.0 (8GT/s) is already sees as a speed limitation for SSD bandwidth. (It can be compared with SAS 12G port that delivers a 12 GT/s data stream). PCIe combined with NVMe will dramatically enhance performance to 16 GT/s per lane.

  • What is new with PCIe 4.0?

There are no encoding changes from 3.0 to 4.0. There were only minor updates in term of protocol. Indeed, evolution to 4.0 is mostly targeted to address the PHY interface. This is expected to be the most challenging issue for designers to solve.

There are also minor changes in terms of link-level management. PCIe 4.0 enables a more robust equalization.

In term of performance, with PCIe 4.0, throughput per lane is 16 GT/s. The link is full duplex, which means the data can be sent and received simultaneously à Total Bandwidth: 32GT/s. No other industry protocol can achieve the bandwidth of the PCIe 4.0 technology (Up to 64 Gbytes/s of total bandwidth for a PCIe 4.0 x16). New emerging interfaces such as: Ethernet 40G/100G, InfiniBand, solid-state drives (SSDs) and flash memory are demanding bigger pipes. These figues make PCIe architecture the only technology solution that achieves this level of performance with minimal new software upgrades.

Pcie 4.0 Specification
  • Why choose PLDA's PCIe 4.0 IP ?
    • For the reliability:
18+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies,a specific focus on PCIe. More than 5700 customers, with several hundred ASIC tapeouts
PCIe 3.0 architecture is already silicon proven in several projects. Proven PCIe 3.0 architecture is preserved to enable easy migration to PCIe 4.0. No interface change is necessary; existing behavior is preserved for seamless integration.
PLDA PCIe Controller IP’s currently uses the PIE-8 specification, enabling easy integration with PCS layers from multiple PHY vendors. PLDA actively participates in PIE-8 2.0 specification update.

Pcie 4.0 Base Specification

  • For the Flexibility:

Flexibility of the supported PIPE Configurations for PCIe 4.0:

• PIPE 16-bit is supported in x1, x2, x4, x8 and x16 with 500MHz PIPE clock at 8Gbps (ASIC)
• PIPE 32-bit is supported in x1, x2, x4, x8 with 500MHz PIPE clock at 16Gbps (ASIC)
• PIPE 64-bit will be supported in x1, x2 and x4 with 250MHz PIPE clock at 16Gbps (ASIC/FPGA)

Flexibility of the core configuration to meet spec evolutions

  • For the supported features:

Pcie 4.0 Specs

Features already proven in 3.0, optimized for the targeted markets of PCIe 4.0

  • Endpoint, root port, switch, dual-mode shared silicon
  • Virtualization-ready with SRIOV and ATS/ARI (networking, datacenter)
  • Multi-function
  • AER and data integrity mechanism
  • Complete power management support: legacy, ASPM L0s/L1, OBFF, L1 PM substate with CLKREQ
  • End-end TLP prefixes
  • Because it is optimized for PCIe 4.0 challenges

Extension Devices:

  • Re-timer devices are expected to become widespread in PCIe 4.0 motherboards and backlanes.
    PLDA IP Core supports Extension Device ECN

Multiple Packets Per Clock Cycle:

PCIe 4.0 throughput requires larger datapaths than previous generations.
PLDA chose a 256-bit datapath since its XpressRICH3 IP, providing a proven solution with two options on the receive side:
  • Normal: Received packets are stored in a receive buffer and the user application can extract them one at a time, at its own pace
  • RXstream: Received packets are output to the application one at a time providing greater control over ordering and processing.
  • ​For the Multi PHY Compliance:

Pcie 4.0 Specs

PLDA’s goal is to provide fully integrated “Controller + PHY” solutions for PCIe 4.0 to our customers, targeting various foundry/process combinations. PLDA’s PHY Interoperability test suite for PCIe 4.0 is available to customers and partners (PHY vendors and ASIC vendors). PLDA is partnering with major PHY vendors to have an integrated PHY/Controller solution.